In comparison with Si-based semiconductors, GaAs-based semiconductors and the like, nitride semiconductors such as GaN and AlGaN have advantages of higher breakdown voltage and excellent heat resistance as well as higher saturated drift velocity of electrons, and thus are expected to be able to provide electronic devices that are excellent in high-temperature operation and high-power operation.
In the HFET that is a kind of electronic device formed using such nitride semiconductors, it is well known to generate a two-dimensional electron gas layer resulting from a heterojunction included in a nitride semiconductor stacked-layer structure, and control electric current between source and drain electrodes by a gate electrode having a Schottky barrier junction with the nitride semiconductor layer.
FIG. 18 is a schematic cross-sectional view of a typical conventional HFET using an AlGaN/GaN heterojunction. In this HFET, sequentially stacked on a sapphire substrate 501 are a low-temperature GaN buffer layer 502, an undoped GaN layer 503, and an n-type AlGaN layer 504. A source electrode 505 and a drain electrode 506 each including stacked layers of a Ti layer and an Al layer are formed on n-type AlGaN layer 504. A gate electrode 507 including stacked layers of a Ni layer, a Pt layer and an Au layer is formed between source electrode 505 and drain electrode 506. The HFET of FIG. 18 is a normally-on-type in which even when the gate voltage is 0V, a drain current can flow due to high density of two-dimensional electron gas generated in a heterointerface between undoped GaN layer 503 and n-type AlGaN layer 504.
When an HFET is used as a power transistor, there sometimes occur safety flaws, in case of power outage for example, in a circuit including a normally-on-type HFET. Therefore, in order that an HFET is used as a power transistor, it must be a normally-off-type in which a current does not flow when its gate voltage is 0V. To satisfy this requirement, Patent Document 1 of Japanese Patent Laying-Open No. 2006-339561 proposes an HFET utilizing a mesa structure and a p-n junction in its gate.